1. Field
Example embodiments relate to a semiconductor memory device and a method of fabricating the same. Other example embodiments relate to a phase change memory device and a method of fabricating the same.
2. Description of the Related Art
Semiconductor memory devices may be classified as volatile memory devices or non-volatile memory devices. Non-volatile memory devices maintain data stored when power is turned off. Non-volatile memory devices are widely used in mobile telecommunication systems, mobile memory devices, auxiliary memories of a digital device and the like.
Extensive research has been performed on memory devices with structures that have non-volatile memory characteristics and increased integration density. This research has lead to the development of a phase change memory device. A unit cell of the phase change memory device may include an access device and a data storage element serially connected to the access device. The data storage element includes a lower electrode electrically connected to the access device and a phase change material layer in contact with the lower electrode. The phase change material layer may be a material layer that electrically switches between an amorphous state and a crystalline state. The phase change material layer may be a material layer that electrically switches between various resistivity states under the crystalline state conditions depending on the provided current.
FIG. 1 is a diagram illustrating a cross-sectional view of a conventional phase change memory device.
Referring to FIG. 1, the conventional phase change memory device includes a lower insulating layer 12 disposed (or positioned) on a desired region of a semiconductor substrate 11. A word line 13 may be disposed (or positioned) on the lower insulating layer 12. An upper insulating layer 15 may cover (or be formed over) the semiconductor substrate 11 having the word line 13. The first and second lower electrodes 17A and 17B may be disposed (or positioned) in the upper insulating-layer 15 and in contact with the word line 13. First and second phase change patterns 18A and 18B may be in contact with the first and second lower electrodes 17A and 17B, respectively. First and second upper electrodes 19A and 19B may disposed (or positioned) on the upper insulating layer 15 and in contact with the first and second phase change patterns 18A and 18B, respectively. The first phase change pattern 18A may be interposed between the first lower electrode 17A and the first upper electrode 19A. The second phase change pattern 18B may be interposed between the second lower electrode 17B and the second upper electrode 19B: The first phase change pattern 18A may be separated from the second phase change pattern 18B.
If a program current flows through the first lower electrode 17A, Joule heat is generated at an interface between the first lower electrode 17A and the first phase change pattern 18A. The Joule heat converts a first transition volume 20A that is a part of the first phase change pattern 18A into an amorphous or crystalline state. Resistivity of the first transition volume 20A in the amorphous state may be higher than that of the first transition volume 20A in the crystalline state. Whether information stored in a unit cell of the phase change memory device is a logic “1” or a logic “0” may be determined by sensing (or detecting) the current that flows through the first transition volume 20A in a read mode. If a program current flows through the second lower electrode 17B, a second transition volume 20B that is a part of the second phase change pattern 18B may be converted into an amorphous or crystalline state.
The smaller the gap between the phase change patterns 18A and 18B, the higher the integration intensity of the phase change memory device. Upper surfaces of the lower electrodes 17A and 17B may be disposed (or formed) at substantially the same level. The phase change patterns 18A and 18B may be spaced apart from each other by a first distance D1. The transition volumes 20A and 20B may be spaced apart from each other by the first distance D1.
The heat generated at an interface between the first lower electrode 17A and the first phase change pattern 18A may be transferred to the second phase change pattern 18B through the upper insulating layer 15. The second transition volume 20B may be converted into an amorphous or crystalline state. The first transition volume 20A may be converted into an amorphous or crystalline state by heat generated at an interface between the second lower electrode 17B and the second phase change pattern 18B. The phase change patterns 18A and 18B may interfere with each other, causing malfunction. There is a limit to reducing the distance between the phase change patterns 18A and 18B.